```
// unit -> module
module counter #(parameter WIDTH = 4) // default parameter
(output\[WIDTH-1:0\] count,
input clk, count\_enable, count\_reset
);
// ------------ internal variables --------------------------
reg\[WIDTH-1:0\] count\_reg; // Store the count. Outputs are always registed.
wire clock\_wire;// To gate the clock during disable.
//-------------- main code -----------------------------------
// Keep the count wired to the output:
assign #1 count = count\_reg;
// Don't count while disabled: clock gating
assign clock\_wire = (count\_enable==1'b1)? clk : 1'b0;
// Do the counter: sequential circuit, async-reset
always@(posedge clock\_wire, posedge count\_reset)
begin
if (count\_reset==1'b1)
count\_reg <= 'b0; // Ignore width.
else count\_reg <= count\_reg + 1'b1;
end
endmodule // counter
```
