[TOC] ## 介绍 Yosys是Verilog RTL综合的框架。它目前具有广泛的Verilog-2005支持，并为各种应用程序领域提供了一组基本的综合算法。所选功能和典型应用： * 处理几乎所有可综合的Verilog-2005设计 * 将Verilog转换为BLIF / EDIF / BTOR / SMT-LIB /简单的RTL Verilog /等等 * 内置的形式检查属性和等效性的方法 * 映射到ASIC标准单元库（自由文件格式） * 映射到Xilinx 7系列和Lattice iCE40 FPGA * 自定义流程的基础和/或前端 通过使用合成脚本组合现有过程（算法）并根据需要通过扩展Yosys C ++代码库添加其他过程，可以使Yosys适于执行任何综合工作。 <br/> Yosys是根据ISC许可（与MIT许可或2子BSD许可类似的GPL兼容许可）许可的免费软件。<br/> 事实上，yosys是一个解释器，就如同python的解释器一样，于是从理论上我们可以在linux使用sheban来写脚本运行！ [文档推荐]([https://www.kutu66.com/GitHub/article\_94386](https://www.kutu66.com/GitHub/article_94386)) ## 在deepin上的安装 **首先安装所需要的依赖项目** ```bash sudo apt-get install build-essential clang bison flex \ libreadline-dev gawk tcl-dev libffi-dev git \ graphviz xdot pkg-config python3 libboost-system-dev \ libboost-python-dev libboost-filesystem-dev zlib1g-dev ``` **安装yosys** 使用一下命令进行安装 ```bash sudo apt-get install yosys ``` ## 关于帮助 对于不同版本的yosys，有些命令可能不同，yosys是一个解释器，可以在终端输入`yosys`进入，然后输入`help`查看支持的命令！  ## 分步说明一个简单的例子 **新建`foo.v`文件，文件内容如下所示** ``` module foo ( input a, input b, input c, output o ); assign o = (a & b) | c; endmodule ``` **终端切换到yosys解释器，终端输入yosys即可** ``` yosys ``` **读入待分析的verilog文件** 当然根据版本的不同可能read要换成 read_verilog. ``` yosys> read -sv foo.v 1. Executing Verilog-2005 frontend. Parsing SystemVerilog input from `foo.v' to AST representation. Generating RTLIL representation for module `\foo'. Successfully finished Verilog frontend. ``` **指出顶层模块** ``` yosys> hierarchy -top foo 2. Executing HIERARCHY pass (managing design hierarchy). 2.1. Analyzing design hierarchy.. Top module: \foo 2.2. Analyzing design hierarchy.. Top module: \foo Removed 0 unused modules. ``` **将设计以Yosys的内部格式写入控制台** ``` yosys> write_ilang 3. Executing ILANG backend. Output filename: <stdout> # Generated by Yosys 0.8 (git sha1 5706e90) autoidx 3 attribute \top 1 attribute \src "foo.v:1" module \foo attribute \src "foo.v:8" wire $and$foo.v:8$1_Y attribute \src "foo.v:8" wire $or$foo.v:8$2_Y attribute \src "foo.v:2" wire input 1 \a attribute \src "foo.v:3" wire input 2 \b attribute \src "foo.v:4" wire input 3 \c attribute \src "foo.v:5" wire output 4 \o attribute \src "foo.v:8" cell $and $and$foo.v:8$1 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a connect \B \b connect \Y $and$foo.v:8$1_Y end attribute \src "foo.v:8" cell $or $or$foo.v:8$2 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A $and$foo.v:8$1_Y connect \B \c connect \Y $or$foo.v:8$2_Y end connect \o $or$foo.v:8$2_Y end ``` **将流程（always块）转换为网表元素并执行一些简单的优化** ``` yosys> proc; opt 4. Executing PROC pass (convert processes to netlists). 4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 4.3. Executing PROC_INIT pass (extract init attributes). 4.4. Executing PROC_ARST pass (detect async resets in processes). 4.5. Executing PROC_MUX pass (convert decision trees to multiplexers). 4.6. Executing PROC_DLATCH pass (convert process syncs to latches). 4.7. Executing PROC_DFF pass (convert process syncs to FFs). 4.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 5. Executing OPT pass (performing simple optimizations). 5.1. Executing OPT_EXPR pass (perform const folding). 5.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\foo'. Removed a total of 0 cells. 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \foo.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \foo. Performed a total of 0 changes. 5.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\foo'. Removed a total of 0 cells. 5.6. Executing OPT_RMDFF pass (remove dff with constant values). 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \foo.. removed 1 unused temporary wires. Removed 0 unused cells and 1 unused wires. 5.8. Executing OPT_EXPR pass (perform const folding). 5.9. Finished OPT passes. (There is nothing left to do.) ``` **使用xdot显示设计网表** ``` yosys> show ``` 显示结果如下：  同样的实现，使用gv可用以下命令实现： ``` yosys> show -format ps -viewer gv ``` **将网表转换为门逻辑并执行一些简单的优化** ``` yosys> techmap; opt 7. Executing TECHMAP pass (map to technology primitives). 7.1. Executing Verilog-2005 frontend. Parsing Verilog input from `<techmap.v>' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. Mapping foo.$and$foo.v:8$1 ($and) with simplemap. Mapping foo.$or$foo.v:8$2 ($or) with simplemap. No more expansions possible. 8. Executing OPT pass (performing simple optimizations). 8.1. Executing OPT_EXPR pass (perform const folding). 8.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\foo'. Removed a total of 0 cells. 8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \foo.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \foo. Performed a total of 0 changes. 8.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\foo'. Removed a total of 0 cells. 8.6. Executing OPT_RMDFF pass (remove dff with constant values). 8.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \foo.. Removed 0 unused cells and 1 unused wires. 8.8. Executing OPT_EXPR pass (perform const folding). 8.9. Finished OPT passes. (There is nothing left to do.) ``` **将设计网表写入新的Verilog文件** ``` yosys> write_verilog synth.v ``` 这样流程基本就结束了！ ## 脚本方式执行 If ABC is enabled in the Yosys build configuration and a cell library is given in the liberty file `mycells.lib`, the following synthesis script will synthesize for the given cell library: ``` # read design read -sv foo.v hierarchy -top foo # the high-level stuff proc; fsm; opt; memory; opt # mapping to internal cell library techmap; opt # mapping flip-flops to mycells.lib dfflibmap -liberty mycells.lib # mapping logic to mycells.lib abc -liberty mycells.lib # cleanup clean ``` ## 简单脚本实现 建立foo.ys文件，内容如下： ``` #!/usr/bin/env yosys read -sv foo.v hierarchy -top foo proc; opt; techmap; opt show write_verilog synth.v ``` 执行脚本可以使用 `yosys foo.ys`执行。<br/> 前面已经说到yosys是一个解释器，那么我们可以为foo.ys添加执行权限，使用`chmod +x foo.ys`,然后就如同在linux上执行bash脚本一样，使用 `./foo.ys`来执行。 ## yosys的web版本 我们有时候学习就只想很快的查看一些RTL或者GATE级的结果，安装环境可能遇到各种问题，在这种情况下，我们可以使用yosys的web版本，链接地址： [yosys的web版本](http://hdl.huangzzk.info/)   ## 链接地址 [yosys github地址](https://github.com/YosysHQ/yosys) [测试源码地址](https://gitee.com/yuan_hp/yosys-test)