[8.1 时序电路中数据的读写](8.1%E6%97%B6%E5%BA%8F%E7%94%B5%E8%B7%AF%E4%B8%AD%E6%95%B0%E6%8D%AE%E7%9A%84%E8%AF%BB%E5%86%99.md) [8.2 从RTL角度来看verilog中=和<=的区别](8.2verilog%E4%B8%AD=%E5%92%8C=%E7%9A%84%E5%8C%BA%E5%88%AB.md) [8.3 case和casez的区别](8.3case%E5%92%8Ccasez%E7%9A%84%E5%8C%BA%E5%88%AB.md) [8.4 关于参数的传递与读取（paramter）](8.4%E5%85%B3%E4%BA%8E%E5%8F%82%E6%95%B0%E7%9A%84%E4%BC%A0%E9%80%92%E4%B8%8E%E8%AF%BB%E5%8F%96%EF%BC%88paramter%EF%BC%89.md) [8.5 关于符号优先级](8.5%E5%85%B3%E4%BA%8E%E7%AC%A6%E5%8F%B7%E4%BC%98%E5%85%88%E7%BA%A7.md)